1. Field of the Invention
The present invention generally relates to non-volatile semiconductor memory devices such as an ERPOM, an EEPROM or a flash memory having a floating gate and, more particularly, to a non-volatile semiconductor memory device with an offset provided between the floating gate and the source region.
2. Description of the Related Art
When an electrically alterable EEPROM or a flash memory is over-erased, the channel underneath the floating gate is placed in a depletion state and conducts a leakage current during a read operation of the other memory cells connected to the same bit line. For this reason, an ETOX (E-prom with Tunnel Oxide) memory cell such as an ordinary EPROM is controlled to ensure that over-erase does not occur by performing chip-by-chip verification or bit-by-bit verification. However, such control is difficult to achieve. Other disadvantages are that a verification circuit should be added to the memory cell and that an erase operation takes a relatively long time. An ETOX flash memory cell has a stacked-gate construction such that the floating gate and the control gate are provided as self-aligned patterns, the gate insulating film serving as a tunnel film on the order of 100.ANG..
In one approach to overcome the aforementioned disadvantage, a floating gate is formed on an tunnel insulating film formed on a channel region between a drain diffusion layer and a source diffusion layer formed on a substrate such that the floating gate is displaced toward a first one of the drain diffusion layer and the source diffusion layer, producing an offset between the floating gate and a second one of the drain diffusion layer and the source diffusion layer. A control gate (or a selection gate) is formed to cover the floating gate via an insulating film. The control gate extends over the floating gate so as to cover a portion of the channel beneath the offset. Such a memory cell comprises a memory channel underneath the floating gate and a selection channel between the edge of the floating gate and the second one of the diffusion layers.
Due to the presence of the selection channel, the device according to the aforementioned approach will not conduct a leak current even if the memory channel is placed in a depletion state.
For example, U.S. Pat. Nos. 5,029,130 and 5,280,446 disclose such a device.
FIG. 1 shows a memory matrix comprising memory cells each having a three-layer polysilicon construction. A common source diffusion layer 4 and a common drain diffusion layer 2 are formed on a silicon substrate so as to be parallel with each other. A floating gate 6 is formed to cover the substrate via a tunnel oxidizing film. The floating gate 6 overlaps a portion of the drain diffusion layer 2 and is offset by a certain distance from the source diffusion layer 4. A control gate 8 is formed to cover the floating gate 6 via an insulating film so as to be parallel with the source diffusion layer 4 and the drain diffusion layer 2. An element separation region 16 separates the channels of the memory cells adjacent to each other in a direction in which the control gate 8 extends.
A band-like selection gate 10 is formed to cover the control gate 8 and the substrate via an insulating film in a direction perpendicular to a direction in which the diffusion layers 2 and 4 extend. A selection channel is formed in a substrate region underneath the selection gate 10 between the edge of the floating gate 6 and the source diffusion layer 4.
In a memory cell having a two-layer polysilicon construction, the control gate also serves as the selection gate. That is, the selection gate 10 of FIG. 1 also serves as the control gate.
FIG. 2 is an equivalent circuit of the memory matrix of FIG. 1. The drain diffusion layer 2 and the source diffusion layer 4 extend so as to be common to a plurality of memory cells. In the illustrated example, the diffusion layer 2 is also common to the memory cells laterally adjacent thereto on respective sides, and the diffusion layer 4 is also common to the memory cells laterally adjacent thereto on respective sides. That is, the diffusion layers 2 and 4 extend so as to be common to a total of 2048 memory cells. The drain diffusion layer 2 is connected to a metal virtual ground (VG) line 12 via a contact hole. The source diffusion layer 4 is connected to a metal bit line 14 via a contact hole. The control gate 8 is formed to be parallel with the direction in which the diffusion layers 2 and 4 extend so as to be common to a plurality of memory cells. The selection gate 10 extends in the direction perpendicular to the direction in which the diffusion layers 2 and 4 extend so as to be common to a plurality of memory cells and to form a word line (WL).
In the memory cell of FIG. 2, the selection gate 10 is disposed so as to cross the control gate 8 so that the drain diffusion layer 2 and the source diffusion layer 4 are common to a relatively large number of memory cells and the number of contacts between the memory diffusion layers 2, 4 and the metal lines 12, 14, respectively, is reduced. Thus, the degree of integration is improved.
In the example of FIGS. 1 and 2, the source diffusion layer 4 is common to the memory cells laterally adjacent thereto on respective sides. Longitudinally, the source diffusion layer 4 is common to a series of 1024 memory cells on one side. The result is that a total of 2048 memory cells are connected to the source diffusion layer 4. That is, 2048 memory cells are connected to one metal bit line 14 to which a sense amplifier for reading data from a memory cell is coupled.
When a large number of memory cells are connected to the bit line, the diffusion capacitance imposed on the bit line is relatively high. Thus, it is difficult to improve the speed of a read operation.
The aforementioned problem is not limited to a memory device provided with memory cells of a three-layer polysilicon construction as shown in FIGS. 1 and 2. The same problem may also occur in a memory device provided with memory cells with a two-layer polysilicon construction.